----------------------------------------------------------------------------------
-- Company: Walla Walla Univeristy
-- Engineer: Jacob Priddy
-- 
-- Create Date:    15:57:08 10/30/2018 
-- Design Name:  Clock DIvider
-- Module Name:    clock_divider - clock_divider_arch 
-- Project Name:  ENGR433 - Lab 5
-- Target Devices: 
-- Tool versions: 
-- Description: This is the description clock divider used in waveform generation.
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clock_divider is
	port(
		clk : in std_logic;
		clk_50khz, clk_5khz : out std_logic
	);
end clock_divider;

architecture clock_divider_arch of clock_divider is
	signal reg_50k, reg_50k_next : unsigned(9 downto 0);
	signal reg_5k, reg_5k_next : unsigned(13 downto 0);
begin
	-- Counter Memory
	process(clk)
	begin
		if (clk'event and clk = '1') then
			reg_50k <= reg_50k_next;
			reg_5k <= reg_5k_next;
		end if;
	end process;
	
	-- Next State Logic
	reg_50k_next <= (others => '0') when reg_50k=999 else reg_50k+1;
	reg_5k_next <= (others => '0') when reg_5k=9999 else reg_5k+1;
	
	-- Output Logic
	clk_50khz <= '1' when reg_50k = 999 else '0';
	clk_5khz <= '1' when reg_5k = 9999 else '0';
end clock_divider_arch;