FPGA initialization when using Quicksim

Or, how to make your flip-flops flop when doing a simulation
This note is specific to Spartan2e FPGA implementations.

Background:
In an actual FPGA there is a circuit that detects power on and asserts a reset signal to the flip flops in each CLB. When simulating, flip-flops don't respond until there is an equivalent assertion of a reset to each. Xilinx has defined a global reset signal that is connected to each flip flop in the xilinx component library. This signal must be asserted briefly at the start of simulation.

Do this:
  1. Draw your schematic in DA as usual. No additional components or ports needed i.e., you shouldn't need a Startup part in your design
  2. Create your viewpoint
  3. Start up Quicksim
  4. Create a force for signal name //globalsetreset (the two slashes are needed). I suggest setting this signal to 0 at time 0, 1 at time 5, and 0 at time 20. The default units of time are nanoseconds.
  5. Other forces can be set to inital values at time 0, but based on the reset assertion suggested above, the flip-flops will not respond until the de-assertion of //globalsetreset at time 20ns. Factor that into your assertion of other forces
  6. Shorter assertion of //globalsetreset may be possible, but needs to be as long as the minimum asynchronous assertion of resets shown in the FPGA data sheet


Larry Aamodt PhD, PE
Professor of Engineering and Computer Science
Walla Walla College
Contact:
via email: AamoLa@wwc.edu
via phone: x2058