library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
-------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity clockgen is
	port (clk : in STD_LOGIC;
			sysclk : out STD_LOGIC);
end clockgen;

architecture behav_clockgen of clockgen is
	constant MAXCOUNT : integer := 25000000;
	signal r_reg: unsigned(25 downto 0);
	signal r_next, r_inc: unsigned(25 downto 0);
	signal c_reg, c_next: STD_LOGIC;
begin
	-- register
	process(clk)
	begin
		if (clk'event and clk='1') then
			r_reg <= r_next;
			c_reg <= c_next;
		end if;
	end process;

	-- next state logic
	r_inc <= r_reg + 1;
	process(r_inc,c_reg)
	begin
		if r_inc=MAXCOUNT then
			r_next <= (others=>'0');
			c_next <= not c_reg;
		else
			r_next <= r_inc;
			c_next <= c_reg;
		end if;
	end process;

	-- output logic
        BUFG_inst: BUFG Port Map (sysclk,c_reg);
end behav_clockgen;